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CPUID32 SYSTEM REPORT |
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| Processor Identity | ||
| Vendor | GenuineIntel | |
| Type | Original OEM Processor | |
| Family | 6 | |
| Model | B [Pentium III Tualatin (0.13 um)] | |
| Long Name | Intel(R) Pentium(R) III Mobile CPU 1000MHz | |
| Stepping | 1 | |
| BRAND ID | Genuine Mobile Intel(R) Pentium(R) III Processor-M | |
| Speed | 996.458 MHz [Normalized to 1000 MHz] | |
| Standard Processor Features | ||
| Built-in Co Processor [FPU] | Yes | |
| Virtual 8086 Mode Extensions [VME] | Yes | |
| Debugging Extension [DE] | Yes | |
| Page Size Extension [PSE] | Yes | |
| Time Stamp Counter [TSC] | Yes | |
| Model Spesific Registers [MSR] | Yes | |
| Physical Address Extension [PAE] | Yes | |
| Machine Check Exception [MCE] | Yes | |
| Compare & Exchange Instruction [CX8] | Yes | |
| Built-in Local APIC | No | |
| Fast System Enter / Call [SEP] | Yes | |
| Memory Type Range Registers [MTRR] | Yes | |
| Page Global Enable [PGE] | Yes | |
| Machine Check Architecture [MCA] | Yes | |
| Conditional Move and Compare Instruction [CMOV] | Yes | |
| Page Attribute Table [PAT] | Yes | |
| 36-bit Page Size Extension [PSE36] | Yes | |
| Processor Serial Number [PSN] | No | |
| Cache Line Flush Instruction Support [CLFLSH] | No | |
| Debug Trace & EMON Store MSRs [DTES] | No | |
| ACPI Technology | No | |
| MMX Technology | Yes | |
| Fast Floating Point Save & Restore [FXSR] | Yes | |
| SIMD Streaming Extensions Technology [SSE] | Yes | |
| SIMD Streaming Extensions 2 Technology [SSE2] | No | |
| Self Snoop [SS] | No | |
| Hyper Threading Technology [HTT] | No | |
| Automatic Clock Control / Thermal Monitor [TM] | No | |
| Intel Architecture for 64-bit processor [IA-64] | No | |
| Pending Break Event [PBE] | No | |
| Context ID for L1 Data Cache | No | |
| Standard Processor Configuration Descriptor | ||
| Data TLB: 4K-byte pages, 4-way set associative, 64 entries | ||
| Instruction TLB: 4M-byte pages, fully associative, 2 entries | ||
| Instruction TLB: 4K-byte pages, 4-way set associative, 32 entries | ||
| L1 Data cache: 16K-bytes, 4-way set associative, 32 byte line size | ||
| Data TLB: 4M-byte pages, 4-way set associative, 8 entries | ||
| L1 Instruction cache: 16K-bytes, 4-way set associative, 32 byte line size | ||
| Unified L2 cache: 512K-bytes, 8-way set associative, 32 byte line size | ||
| Benchmark Result | ||
| Dhrystone ALU [7500000 iterations] | 1901.1407 MIPS | |
| Whetstone ALU [7500 iterations] | 5.1653 MWIPS | |
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Generated by CPUID32 v1.32 Copyright © Bayu Prasetio, 2000 - 2003 |
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