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CPUID32 SYSTEM REPORT |
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| Processor Identity | ||
| Vendor | GenuineIntel | |
| Type | Original OEM Processor | |
| Family | F | |
| Model | 2 [Pentium 4 Northwood (0.13 um)] | |
| Long Name | Intel(R) Pentium(R) 4 CPU 2.66GHz | |
| Stepping | 7 | |
| BRAND ID | Genuine Intel(R) Pentium(R) 4 processor | |
| Speed | 2658.041 MHz [Normalized to 2667 MHz] | |
| Local APIC Physical ID | 08 | |
| Cache Line FLUSH [CLFLUSH] Size | 64 | |
| Standard Processor Features | ||
| Built-in Co Processor [FPU] | Yes | |
| Virtual 8086 Mode Extensions [VME] | Yes | |
| Debugging Extension [DE] | Yes | |
| Page Size Extension [PSE] | Yes | |
| Time Stamp Counter [TSC] | Yes | |
| Model Spesific Registers [MSR] | Yes | |
| Physical Address Extension [PAE] | Yes | |
| Machine Check Exception [MCE] | Yes | |
| Compare & Exchange Instruction [CX8] | Yes | |
| Built-in Local APIC | Yes | |
| Fast System Enter / Call [SEP] | Yes | |
| Memory Type Range Registers [MTRR] | Yes | |
| Page Global Enable [PGE] | Yes | |
| Machine Check Architecture [MCA] | Yes | |
| Conditional Move and Compare Instruction [CMOV] | Yes | |
| Page Attribute Table [PAT] | Yes | |
| 36-bit Page Size Extension [PSE36] | Yes | |
| Processor Serial Number [PSN] | No | |
| Cache Line Flush Instruction Support [CLFLSH] | Yes | |
| Debug Trace & EMON Store MSRs [DTES] | Yes | |
| ACPI Technology | Yes | |
| MMX Technology | Yes | |
| Fast Floating Point Save & Restore [FXSR] | Yes | |
| SIMD Streaming Extensions Technology [SSE] | Yes | |
| SIMD Streaming Extensions 2 Technology [SSE2] | Yes | |
| Self Snoop [SS] | Yes | |
| Hyper Threading Technology [HTT] | Yes | |
| IA-32 Thermal Monitor Supported [TM] | Yes | |
| Intel 64-bit Processor Architecture [IA-64] | No | |
| Pending Break Event [PBE] | Yes | |
| SIMD Streaming Extensions 3 Technology [SSE3] | No | |
| MONITOR / MWAIT Instruction [MONITOR] | No | |
| CPL - Qualified Debug Store Feature [DS-CPL] | No | |
| Enhanced SpeedStep Technology [EST] | No | |
| IA-32 Thermal Monitor 2 Supported [TM2] | No | |
| Context ID for L1 Data Cache [CNXT-ID] | Yes | |
| Standard Processor Configuration Descriptor | ||
| L1 Data cache: 8K-bytes, 4-way set associative, dual-sectored line, 64-byte sector size | ||
| Data TLB: 4K or 4M pages, fully associative, 64 entries | ||
| Instruction TLB: 4K, 2M or 4M pages, fully associative, 128 entries | ||
| Unified L2 cache: 512K-bytes, 8-way set associative, dual-sectored line, 64-byte sector size | ||
| L1 Instruction Trace cache: 12K-uops, 8-way set associative | ||
| No L2 cache (P6 family), or No L3 cache (Pentium 4 and Xeon processors) | ||
| Benchmark Result | ||
| Dhrystone ALU [20000000 iterations] | 5120.3277 MIPS | |
| Whetstone ALU [20000 iterations] | 6.3072 MWIPS | |
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Generated by CPUID32 v1.33 - 2003/6/10-22:25:19.437 Copyright © Bayu Prasetio, 2000 - 2003 |
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