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CPUID32 SYSTEM REPORT |
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| Processor Identity | ||
| Vendor | AuthenticAMD | |
| Type | Original OEM Processor | |
| Family | 6 | |
| Model | 6 [K7 Athlon Palomino (0.18 um)] | |
| Long Name | AMD Athlon(tm) XP 1500+ | |
| Stepping | 2 | |
| Speed | 1333.381 MHz [Normalized to 1333 MHz] | |
| Standard Processor Features | ||
| Built-in Co Processor [FPU] | Yes | |
| Virtual 8086 Mode Extensions [VME] | Yes | |
| Debugging Extension [DE] | Yes | |
| Page Size Extension [PSE] | Yes | |
| Time Stamp Counter [TSC] | Yes | |
| Model Spesific Registers [MSR] | Yes | |
| Physical Address Extension [PAE] | Yes | |
| Machine Check Exception [MCE] | Yes | |
| Compare & Exchange Instruction [CX8] | Yes | |
| Built-in Local APIC | No | |
| Fast System Enter / Call [SEP] | Yes | |
| Memory Type Range Registers [MTRR] | Yes | |
| Page Global Enable [PGE] | Yes | |
| Machine Check Architecture [MCA] | Yes | |
| Conditional Move and Compare Instruction [CMOV] | Yes | |
| Page Attribute Table [PAT] | Yes | |
| 36-bit Page Size Extension [PSE36] | Yes | |
| Processor Serial Number [PSN] | No | |
| Cache Line Flush Instruction Support [CLFLSH] | No | |
| Debug Trace & EMON Store MSRs [DTES] | No | |
| ACPI Technology | No | |
| MMX Technology | Yes | |
| Fast Floating Point Save & Restore [FXSR] | Yes | |
| SIMD Streaming Extensions Technology [SSE] | Yes | |
| SIMD Streaming Extensions 2 Technology [SSE2] | No | |
| Self Snoop [SS] | No | |
| Hyper Threading Technology [HTT] | No | |
| Automatic Clock Control / Thermal Monitor [TM] | No | |
| Intel Architecture for 64-bit processor [IA-64] | No | |
| Pending Break Event [PBE] | No | |
| Context ID for L1 Data Cache | No | |
| Extended Processor Identity | ||
| Family | 7 | |
| Model | 6 [K7 Athlon Palomino (0.18 um)] | |
| Long Name | AMD Athlon(tm) XP 1500+ | |
| Stepping | 2 | |
| Extended Processor Features | ||
| Built-in Co Processor [FPU] | Yes | |
| Virtual 8086 Mode Extensions [VME] | Yes | |
| Debugging Extension [DE] | Yes | |
| Page Size Extension [PSE] | Yes | |
| Time Stamp Counter [TSC] | Yes | |
| Model Spesific Registers [MSR] | Yes | |
| Physical Address Extension [PAE] | Yes | |
| Machine Check Exception [MCE] | Yes | |
| Compare & Exchange Instruction [CX8] | Yes | |
| Built-in Local APIC | No | |
| Fast System Enter / Call [SEP] | Yes | |
| Memory Type Range Registers [MTRR] | Yes | |
| Page Global Enable [PGE] | Yes | |
| Machine Check Architecture [MCA] | Yes | |
| Conditional Move and Compare Instruction [CMOV] | Yes | |
| Page Attribute Table [PAT] | Yes | |
| 36-bit Page Size Extension [PSE36] | Yes | |
| Multi Processing Capable [MP] | Yes | |
| No Execute on Stack Pages [NX] | No | |
| Extended MMX / MMX+ [SSE-MMX/MEM] Technology | Yes | |
| MMX Technology | Yes | |
| Fast Floating Point Save & Restore [FXSR] | Yes | |
| 64-bit Long Mode AMD Architecture | No | |
| Extended 3DNow! Technology | Yes | |
| 3DNow! Technology | Yes | |
| L1 Cache and TLB Configuration | ||
| L1 Data TLB, 4M/2M pages | 4 ways, 8 entries | |
| L1 Code TLB, 4M/2M pages | full, 8 entries | |
| L1 Data TLB, 4K pages | full, 32 entries | |
| L1 Code TLB, 4K pages | full, 16 entries | |
| L1 Data Cache | 64 KB, 2 ways, 1 lines per tag, 64 byte lines | |
| L1 Code Cache | 64 KB, 2 ways, 1 lines per tag, 64 byte lines | |
| L2 Cache and TLB Configuration | ||
| L2 Data TLB, 4K pages | 4 ways, 256 entries | |
| L2 Code TLB, 4K pages | 4 ways, 256 entries | |
| Unified L2 Cache | 256 KB, 16 ways, 1 lines per tag, 64 byte lines | |
| Enhanced Power Management | ||
| Temperature Sensing Diode Support | Yes | |
| Frequency ID controll Support [FID] | No | |
| Voltage ID Controll Support [VID] | No | |
| Physical Address And Linear Address Size | ||
| Physical Address Size | 34-bits [approx. 17179869184 bytes] | |
| Linear Address Size | 32-bits [approx. 4294967296 bytes] | |
| Benchmark Result | ||
| Dhrystone ALU [7500000 iterations] | 3213.3676 MIPS | |
| Whetstone ALU [7500 iterations] | 6.6313 MWIPS | |
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Generated by CPUID32 v1.32 Copyright © Bayu Prasetio, 2000 - 2003 |
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